The present invention relates to a MOS type transistor and a configuration and manufacturing method of a semiconductor integrated circuit device containing it, and more particularly to its structure for preventing electrostatic discharge. Hereinafter the electrostatic discharge (destroy) will be abbreviated as ESD.
FIG. 50 is a block diagram showing a typical prior art input protection circuit against ESD. To protect an internal circuit (CMOS inverter in the initial stage) 5010 from ESD from an input terminal 5001, an input protection circuit 5007 is structured by a diode D.sub.1 5005 connected to a resistor R 5002 and a signal line V.sub.dd 5003 and a diode D.sub.2 5005 connected to GND (called an earth or V.sub.ss). The CMOS inverter comprises an N-channel type MOS transistor 5009 (hereinafter referred to as an NMOS transistor) and a P-channel type MOS transistor 5008 (PMOS transistor). An arrow 5011 indicates a signal line connected to a circuit further inside. Such structure is the main stream.
The technology described above has the following problems.
FIG. 51 is a graph showing a characteristic (I-V characteristic) between voltage and current of the diode in the reverse direction used in the prior art protection circuit. A withstand voltage V.sub.R of the diode approaches to a withstand voltage BV.sub.OX of a gate insulating film (called as gate SiO.sub.2 or gate OX, etc.) of the MOS transistor when the current I.sub.R reaches to the level of about 100 mA, even if V.sub.R has been set lower than BV.sub.OX when I.sub.R is in the level of 1 nA or 1 .mu.A. In the description below, as against CMOS semiconductor integrated circuit devices (IC) used in the standard of 5V of V.sub.dd, those used in more than 10 V, 12 V or more than 16 V and 24 V will be described as high withstanding CMOS ICs.
When the high withstanding CMOS is used, it is necessary to increase a withstand voltage of the diode by some degrees and the gate OX has become thin in the advancement of refinement (BV.sub.OX has been lowered). Accordingly, the margin for protecting the internal circuit has come to be reduced.
It is noted that for ESD immunity presently used, a machine model 200 PF, 0 .OMEGA. series resistance and 400 V (meaning that IC will not be destroyed by min. 400 V; normally 200 to 400 V is the criterion) become one of criteria in the EIAJ standard.
When a pulse width at this time is about 100 nsec., a flowing current is represented as follows: ##EQU1##
ESD is a short time high current event.
Although there is a human model loaded with a series resistance (a standard and device charge model often used in the U.S.) as another notation of ESD immunity, the machine model which is common in Japan will be explained in the present invention since it is fully correlated qualitatively with the EIAJ standard described above.
If the resistor R in FIG. 50 is increased for example to restrict I entering the diode, it then takes a large area, causing a problem in the high integration. It is because the volume is also an important parameter, beside the resistance value itself, and hence it requires an area which far exceeds the initial expectation.
The withstand voltage of the diode is normally about 20 to 30 V in a CMOS IC. If the withstand voltage is tried to be increased in a case of LOCOS (Local Oxidation of Silicon: the generic name of processes in the field separation method which is presently the main stream) process, although the field dope (concentration of an impurity layer under a thick oxide film in a field separation area in the case of LOCOS) has to be densified, there arises a problem of inviting either or all of the increase of capacity of junctions and wires, the induction of crystal defects, the increase of processes and the drop of the narrow channel effect.
Accordingly, there is a problem in the aspect of protecting other circuits in the end even if the ESD immunity of the diode itself is increased.